GFET-S10 for Sensing applications
GFET-S10 (Die size 10 mm x 10 mm) - Processed in Clean Room Class 1000
The GFET-S10 chip from Graphenea provides 36 graphene devices distributed in a grid pattern on the chip. Thirty devices have a Hall-bar geometry and six have a 2-probe geometry. The Hall-bar devices can be used for Hall-bar measurements as well as 4-probe and 2-probe devices. There are varying graphene channel dimensions to allow investigation of geometry dependence on device properties.
- · Growth method: CVD synthesis
- · Chip dimensions: 10 mm x 10 mm
- · Chip thickness: 675 μm
- · Number of GFETs per chip: 36
- · Gate oxide thickness: 90 nm
- · Gate oxide material: SiO2
- · Resistivity of substrate: 1-10 Ω.cm
- · Metallization: Nickel/Aluminium 140 nm
- · Graphene field-effect mobility: >1000 cm2/V.s
- · Residual charge carrier density: <2 x 1012 cm-2
- · Dirac point: 10-40 V
- · Minimum working devices: >75 %
Absolute maximum ratings
- · Maximum gate-source voltage: ± 50 V
- · Maximum temperature rating: 150 °C
· Maximum drain-source current density 107A.cm-2
All our samples are subjected to a rigorous QC in order to ensure a high quality products.
- · Optical Microscopy inspection of all devices
- · Raman Spectroscopy of each fabrication batch
- · Electrical characterisation of each fabrication batch
Graphene field-effect transistors (GFETs) have unprecedented sensitivity to the surrounding environment and is an ideal transducer for a variety of sensing applications. Depending on the application, GFETs can be tuned to be sensitive only to the stimulus of interest and have shown breakthrough performance in areas such as photosensing, magnetic sensing and biosensing.
“Graphene field effect transistors on flexible substrate: Stable process and high RF performance"; DOI: 10.1109/EuMIC.2016.7777516
“High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide", Scientific Reports volume 7, Article number: 2419(2017) doi:10.1038/s41598-017-02541-2
Frequently Asked Questions
A: There are a number of common reasons if no current flow is observed in the graphene device. We suggest going through the following points in sequence.
1. Check the electrical connection and setup is working as expected. Lift the source and drain probes from the GFET device and re-position the probes onto a metallic pad so that the probes are electrically shorted via the metallic pad. Apply 10mV between the tips and check that the current is of the order of mA, if the current is much lower than this then there is a problem with the setup either in the electrical measurement system, in the cabling or the probe tips are dirty and may need replacing.
2. If the setup is functioning correctly then put the probes in contact with the source and drain device pads and check the current through the graphene channel. Initially apply 10mV between the source and drain. If the current level is less than 1 μA then the graphene channel itself might be damaged.
If the above checks are unsuccessful then it is likely that the graphene channel itself has been damaged.
A: In normal operation, varying the gate voltage modulates the Fermi energy of charge carriers within the graphene channel. The density of states is a function of the Fermi energy and leads to the gate voltage controlling the conductance of the graphene channel. If no such modulation of the conductance is observed then it is possible that the gate voltage is not being successfully applied. This can be due to a problem in the electrical connection to the gate (the Si substrate) or could be due to excessive leakage current between the gate and the graphene channel. Gate leakage can be due to electrical breakdown of the gate dielectric material and can occur between the substrate and the graphene directly or between the substrate and either one of the electrical contacts to the graphene channel.
The gate leakage current should be <1 nA in normal operation and values above this will compromise the device performance.
A: Graphene on SiO2 is often p-doped as a result of trapped charge impurities in the substrate and absorbed species on the surface of the graphene. Exposure to air leads to the adsorption of water molecules with the effect that the Dirac point is shifted to positive gate voltages and can cause the Dirac point to be located out of the recommended gate voltage range. An annealing process can be applied to reduce this intrinsic doping and consequently shift the Dirac point to lower gate-source voltages. We recommend a thermal annealing at 150 ºC for several hours in inert atmosphere, and/or a current annealing with relatively large currents (of the order of 108 A/cm2).
In addition, storage of the chips in a low humidity environment (N2 cabinet, desiccator, or vacuum) is highly recommended.
A: Typically, when measuring GFETs in air, a large hysteresis is observed between the forward and backward sweeps of a transfer curve. Hysteresis is due to charging and discharging of charge traps in the vicinity of the graphene channel; as the energy of the carriers in the graphene are changed during the transfer curve measurement, different trap sites at different energy levels are populated and depopulated. The origin of the trap sites ispredominantly due to surface adsorbates and annealing processes as described above can be applied to reduce the hysteresis. Other sources of charge trapping are in the gate dielectric.
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