GFET-S10 (Die size 10 mm x 10 mm) - Processed in Clean Room Class 1000
The GFET-S10 chip from Graphenea provides 36 graphene devices distributed in a grid pattern on the chip. Thirty devices have a Hall-bar geometry and six have a 2-probe geometry. The Hall-bar devices can be used for Hall-bar measurements as well as 4-probe and 2-probe devices. There are varying graphene channel dimensions to allow investigation of geometry dependence on device properties.
The new version replaces Ni/Al contacts by Cr/Au, which are more inert and stable.
- · Growth method: CVD synthesis
- · Chip dimensions: 10 mm x 10 mm
- · Chip thickness: 675 μm
- · Number of GFETs per chip: 36
- · Gate oxide thickness: 90 nm
- · Gate oxide material: SiO2
- · Dielectric Constant of the SiO2 layer: 3.9
- · Resistivity of substrate: 1-10 Ω.cm
- · Metallization: Chromium/Gold 2/50nm
- · Graphene field-effect mobility: >1000 cm2/V.s
- · Dirac point: <50 V
- · Minimum working devices: >75 %
Absolute maximum ratings
- · Maximum gate-source voltage: ± 50 V
- · Maximum temperature rating: 150 °C
- · Maximum drain-source current density 107A.cm-2
All our samples are subjected to a rigorous QC in order to ensure a high quality products.
- · Optical microscopy inspection of all the devices
- · Raman Spectroscopy of each fabrication batch
- · Electrical characterisation of each fabrication batch
Graphene field-effect transistors (GFETs) have unprecedented sensitivity to the surrounding environment and is an ideal transducer for a variety of sensing applications. Depending on the application, GFETs can be tuned to be sensitive only to the stimulus of interest and have shown breakthrough performance in areas such as photosensing, magnetic sensing and biosensing.
“Graphene field effect transistors on flexible substrate: Stable process and high RF performance"; DOI: 10.1109/EuMIC.2016.7777516
“High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide", Scientific Reports volume 7, Article number: 2419(2017) doi:10.1038/s41598-017-02541-2