Bilayer Graphene on SiO2/Si (10 mm x 10 mm)
Bilayer Graphene on SiO₂/Si 10 mm x 10 mm (non AB Bernal stacking) - Processed in Clean Room Class 1000
The bilayer graphene product consists of two CVD layers produced by multiple transfer on a SiO2/Si substrate. Lower sheet resistance values can be obtained when compared to monolayer samples. The product can be prepared in other substrate if required (PET, Quartz).
- · Transparency: >94 %
- · Color: Transparent
- · Coverage: >95%
- · Number of graphene layers: 2
- · Thickness (theoretical): 0.69 nm
- · Sheet resistance: 190±30 Ohms/sq (1cm x 1cm)
- · Grain size: Up to 10 μm
- · Dry Oxide Thickness: 300 nm (+/-5%)
- · Type/Dopant: P/Bor
- · Orientation: <100>
- · Resistivity: <0.005 Ohm·cm
- · Thickness: 525 +/- 20 μm
- · Front surface: Single Side Polished
- · Back Surface: Etched
- · Particles: <firstname.lastname@example.org μm
Our Graphene Oxide is subjected to a rigorous QC in order to ensure a high quality and reproducibility.
- · Transparent conductors in OLEDs, LEDs, solar cells, etc...
- · Graphene transistors and electronic applications
If your application requires more specific quality control, please do not hesitate to contact us.
“Graphene Position Paper, Nanonewsletter”, December 2011
By F. Bonaccorso, J. Coraux, C. Ewels, G. Fiori, A. C. Ferrari, J-C. Gabriel, M. Garcia-Hernandez, J. Kinaret, M. Lemme, D. Neumaier, V. Palermo, A. Zenasni, S. Roche
NOTE: "The impurity levels are higher that in monolayer films due to multiple transfer process"
Frequently Asked Questions
A: It has to be done under dry conditions. When using wafers such as Si or quartz a diamond pen can be used to cleave it. In order to protect the graphene film from debris, we recommend doing it with the protective PMMA layer on top of graphene. In this case, we can provide you the sample with the PMMA on top.
When using thin substrates such as PEN or PEN you can easily cut them using scissors.
A: In principle, additional cleaning is not needed and you can use our graphene directly. However, thermal annealing can be applied, typically at 250-400C under inert atmosphere in order to have a cleaner graphene and to reduce absorbents on the graphene surface.
A: Our graphene on SiO2 is p-doped, with a charge carrier density of around 1013 cm-2. This intrinsic doping can be reduced by at least one order of magnitude by thermal treatments, which lower the Dirac voltage down to 40-80 V. Another alternative is using a passivation layer on top of the graphene, which prevents the presence of water between the substrate and the graphene film.
Questions and answers about this Product
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